A. Field of the Invention
The invention relates to semiconductor circuits and devices. More particularly, the invention relates to low powered semiconductor storage circuits and memories.
B. Description of the Prior Art
Semiconductor memory circuits of the type described in U.S. Pat. No. 3,560,764 issued Feb. 2, 1971 and assigned to the present assignee save power but are burdened by (1) drivers for power gating terminals as well as bit and word lines, (2) different driver voltage levels for operating isolating and load transistors, and (3) additional wiring to support the voltage distribution lines for operating the isolating and load transistors which reduces storage area in a chip. As semiconductor memory density requirements increase, it is desirable to further lower power requirements, decrease circuit area and simplify operation to achieve memory performance suitable for operation with high performance data processing systems.
An object of the invention is a storage circuit that permits the fabrication of high density random access memories.
Another object is a random access memory that is powered without the use of a power gating terminal.
Another object is a random access memory that does not require a special deselect potential for each storage circuit.
Still another object is a memory that has low power requirements by the absence of power gating drivers and accompanying wiring.
In an illustrative embodiment of the invention, a memory storage circuit includes first and second sets of transistors, one set of transistors serving as storage devices and the other set serving as load devices for the storage devices. The storage and load devices operate at different threshold voltages. In one form, the storage devices are of the enhancement type either N or P channel while the load devices are of the depletion type, either N or P type. The storage devices are cross coupled between their respective drain and gate terminals. Each load device is coupled to a different cross coupled transistor. The load devices are also connected to a common voltage supply, the return to the voltage supply being through the cross coupled transistors. An isolating transistor of the first type is connected to each cross coupled transistor. The storage circuit is disposed in a matrix array of word and bit lines. The isolating transistors of the storage circuit are connected to adjacent bit lines in a column. A word line is connected to (a) the gate of all isolating transistors in the same row and (b) the gates of the load devices for the storage circuits in the row. In the storage condition of the circuit, the word line is at a first potential which places the isolating devices in a non-conducting condition and disconnects the cell from the bit lines. The threshold voltage for the load devices, however, is below the word line potential which permits them to supply current to the cross coupled cells from the power supply to retain the information stored in the circuit. The word line potential is changed to a second level for a READ operation. The isolating transistors are turned on by the word line potential to connect the storage cell to the bit lines. Also, the word line potential drives the load transistors further into conduction to supply the parasitic capacitance of the conducting transistor which otherwise would be charged by one bit line. The capacitance on the other bit line is discharged to ground through the conducting transistor. The potentials appearing on the bit lines are subtracted from each other in a differential or sense amplifier to give a resultant pulse indicative of the information state of the cell. To change the information state or WRITE into the storage cell, the word line is changed to the second level while the bit line potentials are changed in opposite directions according to the information state desired to be stored in the circuit. For a binary 1 state, the potentials on the bit lines turn on one and turn off the other storage transistor. One bit line potential charges the parasitic capacitance of one storage transistor to place it in a conducting condition. The other bit line potential discharges the parasitic capacitance of the other storage transistor to place it in a non-conducting condition. To write a binary 0 into the storage circuit, the word line potential is raised to the second level and the bit line potentials are reversed to turn off the conducting transistor and turn on the non-conducting transistor while discharging and charging the appropriate parasitic capacitances in the circuit.
A feature of the invention is a storage circuit including sets of transistors having different threshold operating voltages, in one form enhance and depletion transistors, to permit the cell to be charged without a power gating terminal.
Another feature is a storage circuit including depletion mode FET transistors as load devices that eliminates the need for word drivers to maintain a minimum deselect potential for a storage circuit.
Another feature is a storage circuit that limits power on a bit line to that necessary for reading and writing into a storage cell.
Another feature is a word line that simultaneously operates the isolating and load devices for operating a storage circuit in a store, read and write mode.